A conventional process step in the manufacturing of integrated circuits and devices involves plating a metal layer on a semiconductor wafer surface using a plating apparatus. Typically, the wafer surface has been previously etched and contains many holes and/or trenches. One goal of wafer plating is to uniformly fill the holes and trenches with a conductive material. However, it is very difficult to uniformly fill the holes and trenches such that no voids exist. It is well known that the existence of the voids results in poor performance and defective devices. After such plating step, a polishing step is typically performed using a polishing apparatus to achieve a generally planar surface on the wafer.
Plating the wafer surface with the conductive material over a seed metal layer has important and broad application in the semiconductor industry. Traditionally, aluminum and other metals are plated as one of many metal layers that make up a semiconductor chip. However, in recent times, there is great interest in copper deposition for interconnects on semiconductor chips, because, compared to aluminum, copper reduces electrical resistance and allows semiconductor chips to run faster with less heat generation, resulting in a significant gain in chip capacity and efficiency. Furthermore, copper is known to be a better conductor than aluminum.
Thin film plating of copper into sub-micron holes and trenches is becoming more difficult in ULSI chip processing, particularly when the feature size is below 0.25 .mu.m with the aspect ratio greater than 5 to 1. Common chemical vapor deposition is being used to fill these holes and trenches etched into silicon substrates. Unfortunately, this process so far has yielded a very high cost for developing and integrating interconnects for ULSI technology.
Accordingly, a more accurate, cost effective, and reliable manner of applying a conductive material to the semiconductor substrate is needed.